An integrator is connected in it and the capacitor discharges into this integrator or a low pass circuit. The circuit charges the capacitor to a certain level. 9V AC can be taken from the TV.The above block diagram shows a frequency to voltage converter. The power supply circuit is shown in Figure 2. Since the converter has a high operating frequency, it is easy to interfere, it is best to seal it with a metal (such as the easy pull can) (pay attention to insulation). Put the RF plug on the TV antenna jack, pick up the tone / video signal, adjust the turns between L1 and L2 with insulator, so that the radio frequency signal is the strongest if the sound is not clear, the B1 core is fine, and finally adjusted VR1 makes the image chrominance and brightness. Third, after the production and debugging, after the component is installed, the VR1 is adjusted in the middle position, plus the power supply, the voltage is about 10 mA, when the shorts of Q1, Q2 are pole, and the current should be there. Q1-Q3 is selected with B>30, FT>600MHz 3DG80, S9018 triode, other component resistance, capacity, as shown in Table 1. With the φ0.1 mm of the enamel wire with φ0.1 mm, the φ0.1 mm is used, and the 6 turns is graded. Second, the component selection L1 with φ0.5 mm enameled wire on the ring of φ0.5 mm around 15, L2 with φ0.5 mm enamel line on the 5 mm round wooden rod around 8, at 4 Tap, B1 is converted in a black and white TV.
The image signal is added to the E pole of Q2 by C16, VRL. Q2 On the one hand, the 38.625 MHz signal multiplier, generates 77.25 MHz image carrier frequency signals falling at the four channel the other party is modulated to modulate the 6.5 MHz frequency band audio signal generated by Q3, generate 83.75 MHz sound carrier frequency signal, and These two carrier frequency signals are output by C9 after mixing.
Q1, C1, C2, C3, C4, L1 constitute a deformable parallel capacitor three-point oscillator (also known as tile oscillator), generating an image carrier frequency signal of 38.625 MHz, and then coupled to the B pole of Q2. First, the circuit principle converter circuit is shown in Figure 1.
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